Evolution of Management Essay Example for Free

Evolution of Management Essay From the Biblical times we find monarchies of the time use some form of management to lord over the great kingdoms such as the Egyptians who used hierarchy management to build the pyramids, Moses leading the Israelites through the desert to the promised land and King David when he was in charge of the kingdom of Israel. In Ancient civilizations, the Roman Empire made use of devolved government to manage the vast empires resources. This was done through governors’ who were in charge of certain areas as we see in the bible during the birth of Jesus Christ. We can find artifacts that in old cities such as Jerusalem where we find aqueducts that give us an idea of how they managed the water resources. Modernization of the world led to cities and towns that brought about the need to manage the resources in order to provide services to the people living within them. We also find management in the church and military before the industrial revolution. The Roman Catholic Church is one example that has had an impact on management as we see in the catholic hierarchy led by the pope and includes cardinals, patriarchs, and bishops. The Military has greatly influenced management through power vested in positions in the chain of command. Management continued to evolve and we find individuals in history who have made contributions to the art of management as we know it; Luka Pacioli was an Italian mathematician considered the father of accounting. He invented the double entry accounting system. Adam Smith was a political economist whose concepts on economics at the beginning of the industrial revolution contributed greatly to management today. Robert Owens, Charles Babbage, Henry Vernum Poor and Henry Robinson Towne are other individuals who were influential to management in this era. With the onset of the industrial revolution, new ways of management came into play as new generations looked to increase productivity of organizations. Classical Era Scientific Management Scientific management was pioneered by Frederick W. Taylor a mechanical engineer who sought to improve industrial efficiency. He saw the need to have management design jobs properly and provide incentives to motivate workers to achieve higher productivity. His ideology was to find the best practice, decompose the task into its constituent elements and get rid of things that do not add value. Taylor’s scientific management gave way to specialization and is considered the basis to many other management systems that came after. Taylor was supported in this new way of management by Henry Gantt who is accredited with the Gantt chart that is widely used for project management. Frank and Lillian Gilbreth were also early advocates of the scientific management system. Through the motion study, Frank sought to make the processes more efficient by reducing the motions while Lillian’s interest was on the human aspect of work. The human aspect of the scientific management principles seek to understand the workers personality and needs. Administrative Management Henri Fayol, was a French engineer and manager of the mines developed the administrative theory of management. He viewed management as an activity common to all human undertakings. He is credited to giving us the first comprehensive functions of management; 1.Planning  2.Organizing 3.Command/Direct 4.Coordinate 5.Control He urged that management was an all encompassing activity that should be taught in schools, colleges and universities. This approach proposed that management is a skill which can be acquired if its principles are understood and rejected the idea that â€Å"managers are born, not made†. Bureaucratic Management A German Sociologist, Max Weber’s approach to management was by focusing on the organizational structure. His views divided organizations into hierarchies with clear lines of authority and control, divided labor such that authority and responsibility are clearly defined and legitimized, organizational officials are appointed and not elected, organization members are selected on the basis of their technical qualification obtained through formal education and training. Organizations are to treat all employees and customers equally and not be influenced by differences. Weber’s principles on organizing can create stable, organized and systematic organizations but make it difficult for the organization to adapt to changing environments and new challenges. Neo-Classical Era Operations Management (Research) Operations management, also known as quantitative management, gives a quantitative basis for decision making. It is characterised by the search for the optimal answer to a problem by using quantitative models. It specially deals with the development of mathematical models to aid in decision making and problem solving. This theory holds that managing is a logical and rationale process, so it can be expressed in terms of mathematical models.

User Interfaces Ic Compiler Computer Science Essay

User Interfaces Ic Compiler Computer Science Essay IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16] 4.2 User Interfaces IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts. The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16] icc1 Figure 4.1 IC Compiler Design Flow [21] For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges. To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides. IC Compiler design flow involves execution of following steps: 1. Set up and prepare the libraries and the design data. 2. Perform design planning and power planning. -Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads. -Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current. 3. Perform placement and optimization. IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations. To perform placement and optimization, use the place_opt core command (or from GUI choose Placement menu and then Core Placement and Optimization sub-menu). 4. Perform clock tree synthesis and optimization. To perform the clock tree synthesis and optimization phase, use the command clock_opt (or choose Clock > Core Clock Tree Synthesis and Optimization in the GUI). IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays. 5. Perform routing and postroute optimization. To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI). As part of routing and postroute optimization, IC Compiler performs global routing, detail routing, track assignment, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the routing and postroute optimization functions for special needs. 6. Perform chip finishing and design for manufacturing tasks. IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing. 7. Save the design. Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16] 4.3 How to Invoke the IC Compiler 1. Log in to the UNIX environment with the user id and password . 2. Start IC Compiler from the UNIX promt: UNIX$ icc_shell The xterm unix prompt turns into the IC Compiler shell command prompt. 3. Start the GUI. icc_shell> start_gui This window can display schematics and logical browsers, among other things, once a design is loaded. 4.4 Preparing the Design IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format. These steps are explained in the following sections: à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Libraries à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Power and Ground Nets à ¢Ã¢â€š ¬Ã‚ ¢ Reading the Design à ¢Ã¢â€š ¬Ã‚ ¢ Annotating the Physical Data à ¢Ã¢â€š ¬Ã‚ ¢ Preparing for Timing Analysis and RC Calculation à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Design 4.4.1 Setting Up the Libraries IC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Logic Libraries: IC Compiler uses logic libraries to provide timing and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs. IC Compiler uses variables to define the logic library settings. In each session, you must define the values for the following variables (either interactively, in the .synopsys_dc.setup file, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries: à ¢Ã¢â€š ¬Ã‚ ¢ search_path Lists the paths where IC Compiler can locate the logic libraries. à ¢Ã¢â€š ¬Ã‚ ¢ target_library Lists the logic libraries that IC Compiler can use to perform physical optimization. à ¢Ã¢â€š ¬Ã‚ ¢ link_library Lists the logic libraries that IC Compiler can search to resolve references. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Physical Libraries: IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your technology library. In addition, these reference libraries define the placement unit tile. The technology files provide information such as the names and characteristics (physical and electrical) for each metal layer, which are technology-specific. The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains several views of the cell, which are used for different physical design tasks. If you have not already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it before working on your design. This section describes how to perform the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Create a Milkyway design library To create a Milkyway design library, use the create_mw_lib command (or choose File > Create Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Open a Milkyway design library To open an existing Milkyway design library, use the open_mw_lib command (or choose File > Open Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Report on a Milkyway design library To report on the reference libraries attached to the design library, use the -mw_reference_library option. icc_shell>report_mw_lib-mw_reference_library design_library_name To report on the units used in the design library, use the report_units command. icc_shell> report_units à ¢Ã¢â€š ¬Ã‚ ¢ Change the physical library information To change the technology file, use the set_mw_technology_file command (or choose File > Set Technology File in the GUI) to specify the new technology file name and the name of the design library. à ¢Ã¢â€š ¬Ã‚ ¢ Save the physical library information To save the technology or reference control information in a file for later use, use the write_mw_lib_files command (or choose File > Export > Write Library File in the GUI). In a single invocation of the command, you can output only one type of file. To output both a technology file and a reference control file, you must run the command twice. à ¢Ã¢â€š ¬Ã‚ ¢ Verifying Library Consistency: Consistency between the logic library and the physical library is critical to achieving good results. Before you process your design, ensure that your libraries are consistent by running the check_library command. [16] icc_shell> check_library 4.4.2 Setting Up the Power and Ground Nets IC Compiler uses variables to define names for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets: à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic0_net By default, IC Compiler VSS as the ground net name. If you are using a different name, you must specify the name by setting the mw_logic0_net variable. à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic1_net By default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable. 4.4.3 Reading the Design IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format. à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in Milkyway Format à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in ASCII Format 4.4.4 Annotating the Physical Data IC Compiler provides several methods of annotating physical data on the design: à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a DEF file To read a DEF file, use the read_def command (or choose File > Import > Read DEF in the GUI). icc_shell> read_def -allow_physical design_name.def à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a floorplan file A floorplan file is a file that you previously created by using the write_floorplan command (or by choosing Floorplan > Write Floorplan in the GUI). icc_shell> read_floorplan floorplan_file_name à ¢Ã¢â€š ¬Ã‚ ¢ Copying the physical data from another design To copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan > Copy Floorplan in the GUI). [16] icc_shell> copy_floorplan -from design1 4.4.5 Preparing for Timing Analysis and RC Calculation IC Compiler provides RC calculation technology and timing analysis capabilities for both preroute and postroute data. Before you perform RC calculation and timing analysis, you must complete the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Set up the TLUPlus files You specify these files by using the set_tlu_plus_files command (or by choosing File > Set TLU+ in the GUI). icc_shell> set_tlu_plus_files -tech2itf_map ./path/map_file_name.map -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/best_settings.tlup à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Back-annotate delay or parasitic data To back-annotate the design with delay information provided in a Standard Delay Format (SDF) file, use the read_sdf command (or choose File > Import > Read SDF in the GUI). To remove annotated data from design, use the remove_annotations command. à ¢Ã¢â€š ¬Ã‚ ¢ Set the timing constraints At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input and output arrival times for each I/O port. This requirement ensures that all signal paths are constrained for timing. To read a timing constraints file, use the read_sdc command (or choose File > Import > Read SDC in the GUI). icc_shell> read_sdc -version 1.7 design_name.sdc à ¢Ã¢â€š ¬Ã‚ ¢ Specify the analysis mode Conditions such as fabrication process, operating temperature, and power supply voltage can vary semiconductor device parameters. You can specify the operating conditions for analysis with the set_operating_conditions command. à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Set the derating factors If your timing library does not include minimum and maximum timing data, you can perform simultaneous minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors. à ¢Ã¢â€š ¬Ã‚ ¢ Select the delay calculation algorithm By default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. [16] 4.4.6 Saving the Design To save the design in Milkyway format, use the save_mw_cel command (or choose File > Save Design in the GUI). [16] CHAPTER 5: Design Planning 5.1 Introduction Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment. Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16] Figure 5.1 IC Compiler Design Planning [21] 5.2 Tasks to be performed during Design Planning à ¢Ã¢â€š ¬Ã‚ ¢ Initializing the Floorplan à ¢Ã¢â€š ¬Ã‚ ¢ Automating Die Size Exploration à ¢Ã¢â€š ¬Ã‚ ¢ Handling Black Boxes à ¢Ã¢â€š ¬Ã‚ ¢ Performing an Initial Virtual Flat Placement à ¢Ã¢â€š ¬Ã‚ ¢ Creating and Shaping Plan Groups à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing Prototype Global Routing à ¢Ã¢â€š ¬Ã‚ ¢ Performing Hierarchical Clock Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing In-Place Optimization à ¢Ã¢â€š ¬Ã‚ ¢ Performing Routing-Based Pin Assignment à ¢Ã¢â€š ¬Ã‚ ¢ Performing RC Extraction à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Analysis à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Budgeting à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Physical Hierarchy à ¢Ã¢â€š ¬Ã‚ ¢ Refining the Pin Assignment 5.3 Initializing the Floorplan The steps in initializing the floorplan are described below. à ¢Ã¢â€š ¬Ã‚ ¢ Reading the I/O Constraints: To load the top-level I/O pad and pin constraints, use the read_io_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Defining the Core and Placing the I/O Pads: To define the core and place the I/O pads and pins, use the initialize_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Rectilinear-Shaped Blocks: Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X. à ¢Ã¢â€š ¬Ã‚ ¢ Writing I/O Constraint Information: To write top-level I/O pad or pin constraints, use the write_io_constraints command. Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Cell Rows: To add cell rows, use the add_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Removing Cell Rows: To remove cell rows, use the cut_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Floorplan Information: To save the floorplan information, use the write_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢Writing Floorplan Physical Constraints for Design Compiler Topographical Technology: IC Compiler can now write out the floorplan physical constraints for Design Compiler Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is: write_physical_constraints -output output_file_name -port_side [16] Figure 5.2 Floor Plan After Initialization [21] 5.4 Automating Die Size Exploration This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view. 5.5 Handling Black Boxes Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan. To handle the black boxes run the following set of commands. set_fp_base_gate estimate_fp_black_boxes flatten_fp_black_boxes create_fp_placement place_fp_pins create_qtm_model qtm_bb set_qtm_technology -lib library_name create_qtm_port -type clock $port report_qtm_model write_qtm_model -format qtm_bb report_timing qtm_bb 5.6 Performing an Initial Virtual Flat Placement The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing. The way to perform an initial virtual flat placement is described below. à ¢Ã¢â€š ¬Ã‚ ¢ Evaluating Initial Hard Macro Placement: No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience. à ¢Ã¢â€š ¬Ã‚ ¢ Specifying Hard Macro Placement Constraints: Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement. Creating a User-Defined Array of Hard Macros Setting Floorplan Placement Constraints On Macro Cells Placing a Macro Cell Relative to an Anchor Object Using a Virtual Flat Placement Strategy Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch Creating Macro Blockages for Hard Macros Padding the Hard Macros à ¢Ã¢â€š ¬Ã‚ ¢ Padding the Hard Macros: To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macros cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macros edges. [16] To set a padding distance (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. à ¢Ã¢â€š ¬Ã‚ ¢ Placing Hard Macros and Standard Cells: To place the hard macros and standard cells simultaneously, use the create_fp_placement command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Floorplan Editing: IC Compiler performs the following floorplan editing operations. Creating objects Deleting objects Undoing and redoing edit changes Moving objects Changing the way objects snap to a grid Aligning movable objects 5.7 Creating and Shaping Plan Groups This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros. The following steps are covered for Creating and Shaping Plan Groups. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Plan Groups: To create a plan group, create_plan_groups command. To remove (delete) plan groups from the current design, use the remove_plan_groups command. à ¢Ã¢â€š ¬Ã‚ ¢ Automatically Placing and Shaping Objects In a Design Core: Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped. To automatically place and shape objects in the design core, shape_fp_blocks command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Padding to Plan Groups: To prevent congestion or DRC violations, one can add padding around plan group boundaries. Plan group padding sets placement blockages on the internal and external edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding. To add padding to plan groups, create_fp_plan_group_padding command. To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Block Shielding to Plan Groups or Soft Macros: When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro. To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command. To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16] 5.8 Performing Power Planning After completed the design planning process and have a complete floorplan, one can perform power planning, as explained below. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Logical Power and Ground Connections: To define power and ground connections, use the connect_pg_nets command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Rings: It is necessary to add power and ground rings after doing floorplanning. To add power and ground rings, use the create_rectangular_rings command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Straps: To add power and ground straps, use the create_power_straps command. à ¢Ã¢â€š ¬Ã‚ ¢ Prerouting Standard Cells: To preroute standard cells, use the preroute_standard_cells command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Low-Power Planning for Multithreshold-CMOS Designs: One can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to reduce overall power consumption substantially because it reduces leakage power as well as switching power. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Network Synthesis: As the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems. By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing. To perform the PNS, one can run the set of following commands. [16] synthesize_fp_rail set_fp_rail_constraints set_fp_rail_constraints -set_ring set_fp_block_ring_constraints set_fp_power_pad_constraints set_fp_rail_region_constraints set_fp_rail_voltage_area_constraints set_fp_rail_strategy à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Power Plan: Once the IR drop map meets the IR drop constraints, one can run the commit_fp_rail command to transform the IR drop map into a power plan. à ¢Ã¢â€š ¬Ã‚ ¢ Handling TLUPlus Models in Power Network Synthesis: Power network synthesis supports TLUPlus models. set_fp_rail_strategy -use_tluplus true à ¢Ã¢â€š ¬Ã‚ ¢ Checking Power Network Synthesis Integrity: Initially, when power network synthesis first proposes a power mesh structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one might discover problem areas in design as a result of automatic or manual cell placement. These areas are referred to as chimney areas and pin connect areas. To Check the PNS Integrity one can run the following set of commands. set_fp_rail_strategy -pns_commit_check_file set_fp_rail_strategy -pns_check_chimney_file set_fp_rail_strategy -pns_check_chimney_file pns_chimney_report set_fp_rail_strategy -pns_check_hor_chimney_layers set_fp_rail_strategy -pns_check_chimney_min_dist set_fp_rail_strategy -pns_check_pad_connection file_name set_fp_rail_strategy -pns_report_pad_connection_limit set_fp_rail_strategy -pns_report_min_pin_width set_fp_rail_strategy -pns_check_hard_macro_connection file_name set_fp_rail_strategy -pns_check_hard_macro_connection_limit set_fp_rail_strategy -pns_report_min_pin_width à ¢Ã¢â€š ¬Ã‚ ¢ Analyzing the Power Network: One perform power network analysis to predict IR drop at different floorplan stages on both complete and incomplete power nets in the design. To perform power network analysis, use the analyze_fp_rail command. To add virtual pads, use the create_fp_virtual_pad command. To ignore the hard macro blockages, use the set_fp_power_plan_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Viewing the Analysis Results: When power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current density values to the database by saving the CEL view that has just been analyzed. à ¢Ã¢â€š ¬Ã‚ ¢ Reporting Settings for Power Network Synthesis and Power Network Analysis Strategies: To get a report of the current values of the strategies used by power network synthesis and power network analysis by using the report_fp_rail_strategy command. [16] 5.9 Performing Prototype Global Routing One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion hot spots that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing. To perform global routing, use the route_fp_proto command. 5.10 Performing Hierarchical Clock Planning This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Clock Planning Options: To set clock planning options, use the set_fp_clock_plan_options command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Clock Planning Operations: To perform clock planning operations, use the compile_fp_clock_plan command. à ¢Ã¢â€š ¬Ã‚ ¢ Generating Clock Tree Reports: To generate clock tree reports, use the report_clock_tree command. à ¢Ã¢â€š ¬Ã‚ ¢ Using Multivoltage Designs in Clock Planning: Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning: With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16] 5.11 Performing In-Place Optimization In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. These optimizations prese

Societies Scapegoat :: essays research papers

Societies Scapegoat   Ã‚  Ã‚  Ã‚  Ã‚  Youth crimes are on a continual rise. It seems that everyday violent offenders keep getting younger and more aggressive. We turn on the news only to hear that a ten year old mugged,shot,stabbed,beat or blew up one of his peers. With crimes on the rise involving children, people begin to look for a cause. Society, when looking for a scapegoat, becomes worse than a blood thirsty lynch mob at a witch trial. Usually the most obvious source of violence within a home is the television. However, in most cases it is not the true cause. With the TV in the forefront of virtually every home in the civilized world, it's no wonder that it's the easiest target for criticism. It's elementary to blame the tube for a child's behavior; it's a quick and easily identified source of violence within a youths confined world. The TV many times is identified as the cause of aggressive acts to avoid dealing with other underlying issues. Society today has an entire array of different afflictions that plague us from day to day. The television is of very little significance alongside the landfill of troubles that influence children today. Besides, trying to get networks to cut out violence and aggression entirely would be like trying to get Jesus Christ to write a top ten list of reasons why Christianity sucks. (It's not going to happen.)   Ã‚  Ã‚  Ã‚  Ã‚  TV is not the reason that our youth courts are filled to capacity with court dockets so hideous you would swear that you were looking at the start of the apocalypse. Television programs are not the reason for the apparent increase in adolescent crime. If you find yourself picking up your kids from the police station all the time, it's not the TV's fault!!! There are no significant consequences for youth crime in our justice system. Maybe we should impose stiffer penalties on violent offenders, instead of more censorship on TV. Kids would not have such a tendency to mug, beat, strangle or shoot their peers if there were tougher consequences for doing so.   Ã‚  Ã‚  Ã‚  Ã‚  The Japanese are responsible for some of the most violent cartoons ever created to date. I mean these things make our R rated movies look like a walk in the park. Japanese cartoons display bloodshed and drug induced murdering sprees as if they were nothing. Even with all this vicious behavior on Japanese televisions, the youth crime and aggressive behavior is one tenth of ours. How can this be? Because the Japanese have adopted a zero tolerance policy for criminal behavior and reprimand criminals with a vengeance.

Essay --

For over twenty years, gun control has been a major topic in the United states. With countless amounts of public shootings taken place, our country is starting to question our second amendment which states â€Å" a well regulated militia, being necessary to the security of a free state, the right of the people to keep and bear arms, shall not be infringed†. It was adopted into the United States Constitution on December 15, 1790. It stated basically that people have the right to keep and bear arms. These rights were thought of as â€Å"natural rights† or â€Å"God given rights†. Written as a reminder to the government that they should not try to stop the people from having this right. Should a person have the right to own a gun for protection? Should we completely take away this right to prevent mass murder shootings in public places? A lot of citizens feel uncomfortable to the fact of not having protection and having their privilege’s taken away due to other people and cruel decisions. Although times have changed from when the amendment was passed on December 15th, 1791, U.S. Citizens still feel it is a mandatory thing to have ownership of guns and have them in their daily lives. Public shootings came about in the early 1700’s when the first shooting took place at Pontiac’s Rebellion school on July 26, 1764. Four Lenape American Indians entered the schoolhouse near what today is Greencastle, Pennsylvania, shot and shilled the schoolmaster, and killed nine or ten children. Shootings such as the ones taken place in Virginia Tech, Colombine High School, Sandy Hook Elementary, the movie theater shooting in Aurora, Colorado; all have effected the country in a drastic sense and really impacted us Americans to take change and mak... ...ll waiting to be passed explaining that expanded background checks on gun owners or potential gun owners was to be done. Turns out the senate squashed that bill. President Obama has pushed for gun restrictions after the devastating shootings that have been happening and blames the senate for the failure to expand background checks. Without the full cooperations from both sides of this debate nothing will ever be solved. Banning weapons is not going to completely stop crime. This has just turned into a war against the rights of the individual stated in the constitution. Stricter gun regulations is not the solution but tougher punishments might be. Gun control is not the answer to this problem and that just needs to be accepted so that crime rate can finally be decreased and everyone can live happy with the fact that something is being done in this situation.

Watching A Disappearing Number in Theater Essay -- Simon McBurney

Choose one production that you have seen and which you particularly enjoyed and discuss the aspects which made it so successful. A Disappearing Number I went to see a Disappearing Number, in the Theater. The production was performed by Complicite and was directed by Simon McBurney. I really enjoyed this performance. I thought that the mixture of maths and romance as well as the structure of the performance by incorporating the past and the present together, was extremely successful. The most successful aspect of the performance for me were the scene changes. I found that the rotation of the blackboard, center stage, where the actors were able to stoop beneath it in order to enter and exit the stage, was an effective touch to this non naturalistic performance. When this was first used, at the end of the first scene, when the characters Ruth and Al left the stage, I thought it didn't quite fit as at the beginning the style was leaning towards realism. But as the play progressed and the acting style became more and more non naturalistic, and this rotation of the black board technique was used more frequently it fitted in really well and became really effective. Later on in the performance when Ramanujan and Hardy are introduced, again the scene changes were quick, swift and rapid. Screens were used to conceal the actors as they came on to the stage and then conceal the other actors as they left the stage. The two different scenes which the screens helped to alternate between were Ramanujan, a remarkable mathematician, living in one of the poorest areas of India and the prominent mathematician, G.H Hardy in Cambridge, two people who were in correspondence with each other. Since each of the scenes were short, the use of t... ...was taken away so suddenly. And pain, for moving on. When Al got to the river the projected image of water is repeated. This recurring image from when Ramanujan dies in the past is brought forward into the present storyline making the link between the past and present even stronger. Because this is a repeated image, the water becomes a metaphor for death, the death of Ramanujan and the death of Ruth and her baby. This scene is a peaceful scene even with this metaphor attached. The audience gets to empathise with Al as he lets go of the past and moves on. Imagery is key in this final scene. The sand that each of the characters pour out from various objects, Al pouring from the cremation box and Ramanujan pouring from his tablet, shows the passing of time. A final connection between the two parts to the performance, the past and the present, the key to the whole play.

Jose Rizal Essay

Many of us know already who Dr. Jose Rizal is. A national hero, a genius, a writer, a scientist and a doctor, these are the first thing that comes to our mind. He is a man with many accomplishments. All his writings and works are still recognized in the whole world. Through reading this paper, you could find out how his life has gone to many challenges and what contribution he left in our country. As a Filipino, we are proud because Dr. Jose Rizal gives all of us inspiration in all the things we do. This term paper will illustrate what his many-sided personalities are, as a physician, poet, novelist, essayist, dramatist, historian, sculptor, architect, musician, linguist, bibliophile, translator, educator, economist, surveyor, engineer, naturalist, archeologist, philologist, inventor, sportsman, magician and prophet. We can say that he is an excellent, talented, and yet a very humble man. He truly was a man of action, he did not only looked over the people nor just tell people what to do, he helped them in their everyday work. Dr. Jose Rizal is our hero, our inspiration, our lesson of the past that we should be a man for our country. The main purpose of this paper is to know about the heroism of Dr. Jose Rizal and present his life, works, and writing in an interesting manner. We’ll find out who are the nine women linked to him and what are the challenges he encounter while he was in exile in Dapitan.

Preferred Education Background for an Accountant

An accountant can be defined as any person who carries out accounting task like preparation and presentation of financial reports to the policy makers so that they can make sound decisions, which will enable the organization to achieve its goals. The scope of the accounting work depends entirely on the size of the organization and the individual’s specialization. It is in this interest therefore this paper is written. The qualification of an accountant varies from one country to another and individual’s specialization but basically it involves some education background and certification by a recognized body Accounting involves many financial calculations like balancing of sheets and therefore it is inevitable for people who are planning to take a career in accounting to be good and to have interest in mathematics, be analytical to compare and interpret fingers easily. Still to be noted here is the importance of good written and spoken English. Preparation, analysis and presentation of financial reports require one to be good in both written and spoken English. Accountants should be able to clearly communicate their ideas and to air their views clearly to the managers and clients. Another important thing in accounting is the general knowledge in law like the business law as well as good understanding and interpretation of business terminologies. This comes in hardy when an individual is involved in tendering or taking contracts on behalf of the organization. Technology is another requirement, which cannot go unmentioned because of its importance in accounting. Accountants should be very familiar with business systems and office automation systems such as the accounting computer packages. Based on the above discussion, accountant as a career requires a minimum of Bachelors degree in business studies or any other field where the above mentioned areas are taught like statistics. Many companies in the modern society need accountants with Masters Degrees in business administration with specialization in accounting. The state requires all accountants to be certified for them to be recognized. The certified public accountant certificate CPA is issued by the state through the state board of accountancy. Some states in America require accountants to be university graduates while others demand some working experience in the field of accounting. The later seems to have been adopted by many states together with the corresponding curriculum changes and therefore it is important to scrutinize the requirements of the sate in which they are planning to register with. Citification involves four sections of CPA examination in all the states which is set and marked by the American institute of certified public accountants. Passing examination in the four sections is important for one to be certified. Although it is not necessary to pass all the four sections exam at once, many states puts a limit of two exams compounded by considerable experience for them to give you credit. It is important to understand that one cannot proceed to the next section before passing the previous sections. In conclusion therefore, accounting is a dynamic and noble career which requires determined people to succeed. It was pointed out that accounting requires individuals of high integrity, high amplitude in mathematics, good written and spoken English and analytical people. It was also discussed that the minimum qualification is a Bachelors degree in business studies or any other relevant courses. Certification is inevitable and involves passing four exams in the four sections.